Electronic assemblies typically comprise a plurality of components, such as semiconductor integrated circuits, including MOSFET power transistors, mounted to a substrate such as a printed circuit board (PCB) or ceramic plate. The substrate can include patterns of conductive elements (e.g., pads, traces, and/or planes) to interconnect the substrate to the components in a predetermined way. There are a variety of ways to create interconnections between the conductive terminations on the components and the conductive elements on a substrate. For example, a semiconductor die can be wire-bonded to a lead-frame and over-molded in a package having a standardized footprint. The lead-frame can include a number of conductive leads that are soldered to pads on the surface of the substrate. Conventional examples of such embodiments include integrated circuits in dual-in-line (“DIP”) and small-outline (“SO”) packages. In such packages, the overall volume of the packaged device is usually significantly greater than the volume of the semiconductor die within the package. For power devices, e.g., low voltage MOSFET power transistors, such packages typically exhibit significant lead interconnect resistance and inductance.
Semiconductor components may also be mounted directly to the substrate. One way to do this, shown in FIGS. 1A and 1B, is to directly connect conductive pads (e.g., pads 10a, 10b, 10c) on the surface of the substrate 12 to interconnection pads (not shown) on the surface of a semiconductor die 14 by use of area array interconnects (e.g., ball-grid array interconnects 16a, 16b, and 16c). The area array interconnects may be made, e.g., of solder or conductive epoxy. Stud bumps may also be used. The assembly method shown in FIG. 1 is sometimes referred to as a “flip-chip” assembly.
For some semiconductor components, a plurality of interconnections on the surface of a die are are made to form a component termination. An example of such a component is a power MOSFET, which can include a plurality (in some cases, many thousands) of active cells, each cell comprising a drain, source and gate termination. The drain terminal of the component can be formed by connecting essentially all of the drain terminals of the active cells together. Likewise, the source and gate terminals can be formed by connecting essentially all of the source and gate terminals of the active cells together.
FIG. 13A shows an example of a vertical DMOS power MOSFET die 200 comprising a ball-grid array of interconnects. A vertical MOSFET comprises a plurality of active cells that carry current vertically within a die (as indicated by the arrow in the Figure labeled “current flow”). A first surface of the die can include a plurality of drain contacts and a second surface comprises a plurality of source and gate contacts. The plurality of low power gate contacts are connected together by metallization (not shown) on the second surface of the die and brought out to a ball-grid gate interconnect contact, e.g., interconnect 205 in FIG. 13A. Individual source contacts are also brought out to an array of ball-grid source interconnects 204 on the second surface of the die 200. The array of drain contacts on the first surface of the die are connected together by a sheet of drain contact metallization 202. One way to package such a device is shown in FIG. 13B. In the Figure, the drain contact metallization 202 is connected (e.g., by solder, not shown) to a conductive frame 206. Ball grid contacts, such as source interconnects 204 on the die 200 and drain interconnects 207 on the frame, extend from the bottom of the assembly comprising the die and the frame. As shown in FIG. 14, the device of FIG. 13B may be mounted to a printed circuit board 209 by connecting the drain interconnects 207 and the source interconnects 204 to drain etch planes 211 and source etch plane 213 on the surface of the board 209 (the gate interconnect is not shown). Fairchild Semiconductor Corporation, South Portland, Me., U.S.A., manufactures a device of the kind shown in FIG. 13A, as part number FDZ201N, “N-channel 2.5 V Specified Power Trench BGA MOSFET.”
Lateral power MOSFET devices are also known. Such devices can include a plurality of active cells comprising drain, source, and gate terminals that are connected in parallel. However, unlike the vertical MOSFET discussed above, the current in the cells of a lateral MOSFET flows horizontally within the die. Thus, all of the gate, source, and drain contacts can reside on the same surface of the die. The packaging and mounting techniques shown in FIGS. 13 and 14 are not adapted for use with such a lateral device, particularly in cases where the source and drain contacts are disposed on the same side of the die.
Lateral power MOSFET devices may provide an effective channel ON state resistance lower than 1000 micro-Ohm within a die measuring 3 mm×3 mm. Owing to the relatively high resistance per square of thin metal interconnect layers available on silicon, proximity of source and drain terminals to all active cells within the die is required to achieve comparably low values of effective device ON state resistance. By distributing across the mounting surface of the die a set of interconnect elements, including a subset of drain interconnect elements and a subset of source interconnect elements with alternating source and drain elements, such as with a high density ball grid array (BGA) having a source and drain ball pitch of 0.5 mm or less, low values of effective device ON state resistance may be retained. However, to take full advantage of the low loss capability of such a device, a substrate or printed circuit board providing a low loss, high density array interconnection is required. The interconnect architecture should achieve a substrate interconnect resistance substantially lower than 500 micro-Ohm to adequately support a lateral power MOSFET device having a 1000 micro-Ohm ON state resistance.
One way to interconnect a plurality of connections disposed on the same side of a die is described with respect to a voltage regulator integrated circuit in Burstein et al., U.S. Pat. No. 6,278,264, “Flip-Chip Switching Regulator.” The method generally consists of arranging individual interconnections on the die so that the ball-grid array forms rows of source and drain connections that are generally parallel to the edges of the die. Linear rows of balls connected to MOSFET drains alternate with generally linear rows of balls connected to MOSFET sources. The substrate onto which the balls are placed comprises interdigitated fingers of conductive etch on the top side of the substrate. The interdigitated fingers of conductive etch connect the alternating rows together so as to create a conductive region on the top side of the substrate that connects together all of the MOSFET sources and another conductive region on the top side which connects together all of the MOSFET drains. However, due, in part, to the resistance per square of copper that may be etched with the required line spacing resolution, the interconnect architecture outlined above gives rise to a high substrate interconnect resistance and losses higher than the acceptable limit specified above.